| | | 4.11 Comparative Architectures |
4.11 Comparative Architectures
This week we will look at a wide variety of different processor types.
We will not be doing any programming, but looking at the different types of
processors that are available and there typical applications.
We will also look at the similarities.
Please note that all of the processors have a common subset of instructions.
ADD
, AND
, OR
, SUB
, and XOR
. All processors
can load and store values to memory, and use constants.
They may have other instructions depending on the hardware support:
MUL
, CALL
, RET
, and DIV
.
- Advanced Micro Devices, AMD OpteronTM (NUMA).
- Analog Devices DSP.
- Intel PentiumTM.
- IBM RISC.
- Microchip Embedded & DSP.
- Freescale Embedded & DSP.
- Texas Instruments Embedded & DSP.
This is NOT an all inclusive list and never will be.
- CISC processors
This is what we have been programming on all semester.
The Intel PentiumTM and the AMD AthlonTM processors are good examples.
- RISC processors
IBM/Apple power processors IBM PowerPCTM 750GX-750FX
- DSP processors
The primary feature of this architecture is the ability to do a single
cycle multiply accumulate for Finite Impulse Response (FIR) filters. It
may have several other features including a reverse carry to assist
Fast Fourier Transforms (FFT).
Texas Instruments (TMS320C62x),
Freescale(DSP563XX), and
Analog Devices (ADSP-BF561 - BlackfinTM) all offer Digital Signal Processors.
Microchip has a low end, low power DSP (dsPIC30Fxxx) in their current product line.
- Embedded systems processors.
We will look at the PIC10F200 series of processors from Microchip.
This series of processors comes in a 6 pin package with a price of around 50 cents.
- Dual/multi-processor/Dual core/HyperthreadingTM (Intel) systems -- SMP
- Dual/multi-processor systems -- Non-Uniform Memory Access (NUMA)
OpteronTM from AMD. Non-Uniform Memory Access.
- Harvard architecture
- Symmetric multiprocessing (SMP), bottlenecks.
- Cache issues
- Single cache
- Instruction/Data cache
- Bus snooping
- Translation Look-aside Buffer, TLB.
- Branch cache
- Speculative execution
- Single Instruction, Multiple Data (SIMD)
- Vector processing
- Multiple execution units
- Pipelining & pipeline flushes.
Instructor: Louis Taber, louis.taber.at.pima at gmail dot com (520) 206-6850
My web site in California
The Pima Community College web site
| | | 4.11 Comparative Architectures |